Level shifters, which receive input signals with smaller signal range and correspondingly convert them to output signals with greater signal range, play important roles in interface circuits. For example, a source driver for driving a display panel, original internal control signals in the chip operate in a signal range between 0 and 2 volts. However, for driving sources of the display panel, a required output signal range expands to be between 0 and 5 volts. To convert between the two signal ranges, level shifters are adopted for converting input signals of 0 to 2 volts to output signals of 0 to 5 volts.
Please refer to FIG. 1 illustrating a prior art relating to level shifter 10. The level shifter 10 includes a pair of (p-channel MOS) transistors TP1, TP2 and another pair of (n-channel MOS) transistors TN1, TN2. An input signal IN is inverted to be another input signal INB, wherein the input signals IN and INB operates between voltages VPP and VSS. The level shifter 10 operates between voltages VGH and VSS, and respectively provides output signals OUT, OUTB from nodes n2 and n1 according to the input signals IN and INB, such that the output signals operate between the voltages VGH and VSS, i.e., a signal range of the output signals OUT and OUTB is expanded to be between the voltages VSS and the voltage VGH. Gates of the transistors TN1 and TN2 respectively receive the input signals IN and INB, and gates of the transistors TP1 and TP2 are respectively coupled to the nodes n2 and n1.
Operation of the level shifter 10 can be briefly describes as follows. When the input signal IN equals the voltage VPP, the input signal INB equals the voltage VSS. Therefore, the transistor TN1 turns on such that the output signal OUTB of the node n1 is kept at the voltage VSS, and the transistor TP2 is turned on so the output signal OUT of the node n2 is kept at the voltage VGH. In contrast, the transistor TN2 and TP1 are turned off.
When the input signal IN transits from the voltage VPP to the voltage VSS and the input signal INB transits from the voltage VSS to the voltage VPP, the transistor TN2 starts to conduct a current In to discharge the node n2, so the output signal OUT of the node n2 can be pulled down to the voltage VSS from the original voltage VGH. However, when the transistor TN2 starts to turn on, the transistor TP2 maintains original turned-on status to conduct a current Ip. Thus, in order to successfully pull down the output signal OUT to the voltage VSS, the current In conducted by the transistor TN2 has to compete against the current Ip conducted by the transistor TP2. Because a source-gate cross voltage of the transistor TP2 equals a voltage difference between the voltages VGH and VSS, and a gate-source cross voltage of the transistor TN2 only equals a voltage difference between the voltages VPP and VSS, the current Ip conducted by the transistor TP2 is quite large. To overcome the current Ip with a greater current In under a lower gate-source cross voltage of the transistor TN2, the level shifter 10 has to enlarge dimensions and layout area of the n-channel MOS transistor TN2 (and TN1), so the transistor TN2 (and TN1) can enhance current driving ability with greater aspect (W/L) ratio. Thus, layout area of the level shifter 10 can not be effectively reduced.
Furthermore, while the input signals transit, the great current conducted by the transistor TP1 induces greater, longer-lasting short-wired current during competition, and therefore characteristics, such as transient power consumption, of the prior art level shifter 10 are impacted.